| 摘要 |
PURPOSE:To shorten the turn-off time and to decrease the switching loss of a FET by applying a reverse bias voltage between a gate and a source when the FET is turned off and discharging rapidly the charge charged in the parasitic capacitance. CONSTITUTION:When a driving signal from a pulse width control circuit 28 goes to a level 1, a transistor(TR) 12 is turned on, a FET 11 is also turned on and a drain-source voltage is rapidly nearly zero. When the driving signal is zero, the TR 12 is turned off and TRs 13, 19 are turned on and the charge voltage of a capacitor 18 is applied between the gate and source of the FET 11 via a TR 19 as a reverse bias voltage. Thus, the charge charged between the gate and source is rapidly discharged and an the FET 11 is turned off rapidly. Consequently, since the drain current is decreased to be rapidly made zero, the switching loss is remarkably reduced. |
