| 摘要 |
PURPOSE:To test a high-speed and a low-speed and an intermediate-speed memory by providing a timing generating means which generates a synchronizing clock, etc., and a control means for respective means. CONSTITUTION:Memory pattern generators (MPG) 2 (2-1...) input an operation basic clock from a timing generator 3 and receive a MPG clock from a clock frequency dividing and distribution signal generator 8 to output memory testing data. The generator 8 supplies a distribution signal for MPG to output switching AND gates (11-1...). An OR gate 12 inputs the outputs of the gates 11 and outputs high-speed pattern data and a waveform generator 30 generates a test waveform to be sent to a memory 31 to be tested. A delay device 32 delays data from the gate 12 and a fail memory 34 fetches the decision result of a comparator 33. An operation mode controller 9, on the other hand, outputs an operation mode control signal and when the control signal is 'L', the OR gates 10-1... signify the distribution signal from the generator 8 to enable the parallel high-speed execution operation of the MPG 2. The output of the MPG 2 is inputted to waveform generators 40 and 50 and memories 41 and 51 to be tested are tested independently of each other.
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