Vector processing apparatus capable of performing iterative operation at a high speed.

摘要

In vector processing apparatus comprising operand vector registers (11a, 12a) each memorizing a plurality of vector operand elements, each of readout units (16a, 17a) successively reads a predetermined number of the vector operand elements out of the respective operand vector registers at a predetermined cycle time. The vector operand elements are supplied to arithmetic logic units (25, 30) from the respective operand vector registers. One of the arithmetic logic units is supplied with result elements from another of the arithmetic logic units. The predetermined number of the result elements are successively written in a result vector register (32a) at the predetermined cycle time by a writing unit (33a). With this vector processing apparatus, it is possible to perform iterative operation in parallel at a high speed under simple control.