发明名称 DITHER PICTURE MAGNIFICATION AND REDUCTION PROCESSOR
摘要 PURPOSE:To solve a problem of deterioration in picture quality by calculating density information of a conversion picture element from a binarizing pattern of a reference picture specified by a specified opening and from the size of opening with a conversion picture element calculation means, binarizing the result and applying magnification and reduction of a dither picture. CONSTITUTION:When 16 reference picture elements being converted picture elements designated via a control circuit 71 are inputted via a shift register 31, a calculation circuit 40 executes the comparison processing between a binarized pattern of the reference picture element segmented by the opening to be reserved with the 1st organic dither gradation pattern, and the coincident binarizing pattern is found and processed. When the coincident binarizing pattern is specified, the circuit 40 counts number of black picture elements in the pattern, multiplies a coefficient in response to the size of the opening resulting from the binarizing pattern coincident with the count, the processing with the density of the conversion picture element is executed and outputted, the circuit 50 adds a minimum value from a signal generating circuit 74 to the density, the circuit 60 binarizes the data according to a threshold level matrix from the circuit 75 to apply magnification and reduction processing to the dither picture.
申请公布号 JPH02248159(A) 申请公布日期 1990.10.03
申请号 JP19890068807 申请日期 1989.03.20
申请人 FUJITSU LTD 发明人 OKADA YOSHIYUKI
分类号 H04N1/393;G06T3/40;H04N1/40;H04N1/405 主分类号 H04N1/393
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