| 摘要 |
A microprocessor includes an initializing section for generating a reset signal, in response to an input reset instruction. A controller outputs a bus acquisition request to the microprocessor, in response to the reset signal output from the initializing section. The microprocessor is reset in response to the reset signal output from the initializing section, and generates a bus acquisition acknowledge in accordance with the bus acquisition request output from the controller, thereby releasing a bus and holding an operation state. The controller initializes a cache directory, using the bus which is released in accordance with the bus acquisition acknowledge from the microprocessor.
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