发明名称 OUTPUT BUFFER, OSCILLATING CIRCUIT, VOLTAGE GENERATING CIRCUIT, FUSE CIRCUIT, SEMICONDUCTOR STORAGE DEVICE INCLUDING THE SAME, AND LAYOUT SYSTEM AND TEST SYSTEM THEREOF
摘要 PURPOSE:To stabilize the pseudo static RAM, and to reduce energy consumption by suitably setting the refresh cycle of the pseudo static RAM at a value approaching the information holding ability of a memory cell. CONSTITUTION:The discharge current of the capacitor of an oscillating circuit such as a refresh timer circuit TMR is stabilized, and since the approximate same parasitic capacity is coupled among a polycrystal silicone resistance, the supply voltage of the circuit and a ground potential, the power source fluctuation can be offset, and the fluctuation of the oscillating frequency of the oscillating circuit caused by a power source bump, etc., can be suppressed. Further since the operational characteristics of the oscillating circuit and a refresh timer counter circuit SRC, the address dependency of the information holding characteristic of the memory cell, etc., can be efficiently tested and confirmed, the refresh cycle of the pseudo static RAM can be suitably set at the value approaching the information holding ability of the memory cell. Thus the operation of the pseudo static RAM can be stabilized, and the energy consumption can be reduced.
申请公布号 JPH02246088(A) 申请公布日期 1990.10.01
申请号 JP19890065842 申请日期 1989.03.20
申请人 HITACHI LTD;HITACHI VLSI ENG 发明人 KAJIMOTO TAKESHI;SHINPO YUTAKA;SATO KATSUYUKI;OGATA SHINKO;KEMIZAKI KANEHIDE;KUBONO SHIYOUJI;KATO NOBUO;MANITA KIICHI;KANEMITSU MICHITARO
分类号 G01R31/26;G01R31/28;G11C11/401;G11C11/403;G11C11/406;G11C11/407;G11C11/408;G11C11/409;G11C11/4093;G11C29/00;G11C29/02;G11C29/14;G11C29/50;H01L21/82;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;H03K3/037;H03K19/096 主分类号 G01R31/26
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