| 摘要 |
PURPOSE:To attain the follow-up even to a high speed action clock of a CPU by granting the break control only in a period during which the CPU outputs an access signal and samples a data bus. CONSTITUTION:A CPU gives an access to a higher rank address based on an address signal 13 and a detecting signal 15 of a comparator 1A. At the same time, the CPU puts a break into a lower rank address is a break is detected from the higher rank address. Thus a gate circuit 1B is added for production of the insertion signals 16 and 17. A break instruction is prepared before the data sample timing and the processing time is secured for control since a break instruction inserting part is controlled with only the memory access information given from the CPU. Thus the follow-up is possible even to a high speed action clock of the CPU. |
