发明名称 BEKUTORU*MASUKUENSUSEIGYOHOSHIKI
摘要 PURPOSE:To use mask vector with high sparsity and to shorten the time of array processing by detecting a specified number of arithmetic inhibition bits succeeding in a mask vector, and jumping over ineffective arithmetic of operands which correspond to the inhibition bits. CONSTITUTION:Every time the execution of arithmetic is indicated through an execution control line 11, a mask read address register 6 adds 1 to a mask register 2 and a mask bit (m) and a skip signal S are outputted to a read mask line 8 and a mask-zero detection line 9 successively. At this time, array operands are read out and supplied from a storage device 1 to an arithmetic unit 3. The arithmetic unit 3 performs arithmetic between operands when the bit (m) is 1 and inhibits the arithmetic when 0. Further, when the signal S is 1 and eight successive bits (m) are all 0, data address registers 12a and 121, and the register 6 go up by eight elements to jump over those bits (m), and the time is adjusted by a delay circuit 10, thus writing data in the storage device 1 correctly.
申请公布号 JPH0241070(B2) 申请公布日期 1990.09.14
申请号 JP19810122024 申请日期 1981.08.04
申请人 HITACHI LTD 发明人 ABE HITOSHI;NAGASHIMA SHIGEO;OMODA KOICHIRO;MURAYAMA HIROSHI
分类号 G06F7/00;G06F7/76;G06F15/78;G06F17/16 主分类号 G06F7/00
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