| 摘要 |
PURPOSE:To obviate the malfunction of the circuit or the reduction in its operating speed by arranging at least two load elements or over in parallel. CONSTITUTION:N-channel MOS transistors(TRs) TR01-TR06 are connected between nodes N01-N06 of an output section and GND and gates receive input signals I1-I6. Resistors R01-R06 by polysilicon arrangement exist among nodes N01-N02, N02-N03, N03-N04, N04-N05, N05-N06. Moreover, P-channel MOS TRs 07, 08 are connected as load elements between the nodes N01, N02 at both ends of the output section and a power supply terminal VDD. A sense inverter connects to the node N06 and an output OUT is extracted. Thus, the potential drop due to wiring resistance while keeping the same current supply capability is limited, then malfunction or the reduction of its operating speed is prevented. |
