| 摘要 |
PURPOSE:To increase the rate of application of code rule violation by selecting the clock frequency of a conversion circuit converting a CMI code into an NRZ code to be twice the clock frequency f0 of the transmission signal, decoding the signal by 2-bit each, retarding the bit by one bit when no synchronization is taken and revising the combination of 2 bits. CONSTITUTION:The clock frequency of a CMI NRZ conversion circuit 107 is 2f0 and a receiver 102 receives the output of a selection circuit 106 selecting either a transmission signal 109 or an output signal being the result of retarding the transmission signal 109 at a 1-bit delay circuit 105 and is provided with a frame synchronizing detection circuit 108 detecting a frame synchronizing state of output signals 115A and 115B of the conversion circuit 107, the detection circuit 108 switches the selection circuit 106 when the output signal 115A is asynchronous to select the output signal 114 of the delay circuit 105. Since it is not required to take block synchronization, the code rule violation is freely inserted. |
