| 摘要 |
PURPOSE: To supply the output of high accuracy regardless of the number of upper and lower adjustment operations by moving a binary point to right when upper adjustment is performed and to left in lower adjustment and reflecting the removal of a protective bit at the time of the upper adjustment and the addition of the protective bit at the time of the lower adjustment. CONSTITUTION: For the binary points of respective (a)-(d) registers 10, 20, 30 and 40, the (c) register 30 is moved to the right of the (d) register 40 for 'n' bits and the (a) and (b) registers 10 and 20 are moved to the right of the (c) register 30 for (n) bits and moved to the right of the (d) register 30 for 2n bits. When the upper adjustment operation is performed, a value (n) is reduced for '1' and the binary point of the (a)-(c) registers 10, 20 and 30 are shifted to the right for '1'. When the lower adjustment operation is performed, the binary points of (a)-(c) registers 10, 20 and 30 are moved to the left for '1'. Further, while the upper adjustment and the lower adjustment are performed, the binary point of the (d) register 40 is not moved. Thus, the output of the high accuracy is made possible. |
