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发明名称
WIRED-AND INPUT STAGE FET LOGIC GATE
摘要
申请公布号
EP0186940(B1)
申请公布日期
1990.09.05
申请号
EP19850307223
申请日期
1985.10.09
申请人
TRW INC.
发明人
SAUNDERS, CHRIS HARRY
分类号
H03K19/017;H03K19/08;H03K19/0952;H03K19/0956;H03K19/20
主分类号
H03K19/017
代理机构
代理人
主权项
地址
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