发明名称 INTEGRATED CIRCUIT DEVICE AND ITS FORMING METHOD
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit device, in which the structure of wiring is designed properly, taking into consideration the area and the consumption current of the circuit or which is suitable for inspection of the connecting state of a connection terminal. SOLUTION: An element power source wiring 2a, connected with a circuit including a plurality of cells 1, an element ground wiring 2b, an integrated power source wiring 3a connected with the element power source wiring 2a, and an integrated ground wiring 3b connected with the element ground wiring 2b are arranged on a first wiring layer. A distribution power source wiring 4a, connected with the integrated power source wiring 3a, and a distribution ground wiring 4b connected with the integrated ground wiring 3b are arranged on an upper wiring layer, which is positioned at a location higher than the first wiring layer. On the basis of the wiring structure formula which shows the relation of a voltage decrease amount of a wiring, the wiring area and the consumed current, and a circuit characteristic formula, which shows the relation between the area of a circuit area and consumed current, in the case that the circuit is subdivided, while the ratio of an area of a circuit and the consumption current is kept constant, the wiring structure is determined.
申请公布号 JP2002261245(A) 申请公布日期 2002.09.13
申请号 JP20010060090 申请日期 2001.03.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KUSUMOTO KEIICHI
分类号 H01L21/3205;H01L21/82;H01L21/822;H01L23/52;H01L23/528;H01L25/065;H01L25/07;H01L25/18;H01L27/04;(IPC1-7):H01L27/04;H01L21/320 主分类号 H01L21/3205
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