| 摘要 |
A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.
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