发明名称 CONTROL DSP ARITHMETIC PROCESSOR
摘要 PURPOSE:To avoid the confliction of processes (multiple interruption) by actuating two digital signal processors DSP alternately and in the processing cycles opposite to each other and deciding each interruption timing based on the switch timing set by an external programmable timer. CONSTITUTION:When an input data switch means 16 and an interruption signal switch means 18 are set a contact A with a signal pulse of a programmable timer 42, a DSP 10 accepts a data receiving interruption process SD1 and a DSP 12 accepts an arithmetic interruption process SA1. Then the DSP 10 and 12 accept the processes SA1 and SD1 respectively when both means 16 and 18 are set at a contact B. In such a way, two DSPs are actuated alternately and in the processing cycles opposite to each other. As a result no conflict (no multiple interruption) is caused among the process SD1, the process SA1, and a DSP holding process SDH respectively.
申请公布号 JPH02213947(A) 申请公布日期 1990.08.27
申请号 JP19890033750 申请日期 1989.02.15
申请人 FUJI ELECTRIC CO LTD 发明人 KAWADA SHINYA
分类号 G06F7/00;G06F9/46;G06F9/48;G06F15/16;G06F15/163;G06F15/177;G06F17/10 主分类号 G06F7/00
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