发明名称 SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CONFIGURATION WITH READ CIRCUIT FOR DEFECTIVE MEMORY CELL
摘要 The semiconductor memory device e.g. RAM, having a redundancy configuration circuit and a read circuit, for a defective cell address comprises a programmable ROM (4) for storing an address of a defective memory cell, a comparison circuit (5) for comparing an input address signal and the content of the programmable ROM to detect an access to the defective memory cell, and a redundant memory cell (7) accessed in place of the defective memory cell in response to the detection of the access to the defective memory cell by the comparison circuit. The semiconductor memory device also comprises an input-buffer circuit including a bipolartransistor to which an external input signal is input, and a second transistor connected to the first so as to form a current switch circuit.
申请公布号 KR900006162(B1) 申请公布日期 1990.08.24
申请号 KR19860005636 申请日期 1986.07.12
申请人 FUJITSU CO., LTD. 发明人 AWAYA DOMOHARU
分类号 G11C11/40;G06F12/14;G11C29/00;G11C29/04;G11C29/18;(IPC1-7):G11C29/00 主分类号 G11C11/40
代理机构 代理人
主权项
地址