| 摘要 |
<p>PURPOSE:To attain the emission of an ES memory and the compression of a circuit scale by converting parallel data synchronized with a first clock signal to serial data synchronized with a second clock signal by using a holding means and a conversion means. CONSTITUTION:Introduced parallel data is held by the holding means 113 synchronizing with the first clock signal, and is outputted to the conversion means 119. The conversion means 119 converts the parallel data supplied from the holding means 113 to the serial data synchronizing with the second clock signal, then, outputs it. Thus, since the parallel data synchronized with the first clock signal can be converted to the serial data synchronized with the second clock signal by using the holding means 113 and the conversion means 119, the ES memory can be omitted, and the circuit scale can be compressed.</p> |
