发明名称 MOS SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To perform a fast operation even under a low source voltage by employing a P-channel depletion type MOS transistor as the driving transistor of a driving circuit for an output load. CONSTITUTION:The source of the P-channel depletion type MOS transistor 3 is connected to a power source VDD, and the gate is connected to the output of a CMOS logic circuit part 1. The drain of an N-channel enhancement type MOS transistor 4 is connected to the drain of the P-channel depression type MOS transistor 3, which forms the output of a load driving circuit 2, and the source is grounded, and the gate is connected to the output of the CMOS logic circuit part 1 with the gate of the P-channel depression type MOS transistor 3. Thereby, since the charge of the output load is performed by the P-channel depletion type MOS transistor 3, the fast operation and an operation under the low source voltage can be performed.
申请公布号 JPH02202118(A) 申请公布日期 1990.08.10
申请号 JP19890021135 申请日期 1989.01.31
申请人 NEC CORP 发明人 OKUMURA KOICHIRO
分类号 H03K17/04;H03K19/0185;H03K19/0948 主分类号 H03K17/04
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