INTEGRATED SEMICONDUCTOR STORE

摘要

In an integrated semiconductor store with a parallel testing facility, the bit lines BL, B &cir& NOt L &cir& NOt of each pair of internal bit lines BL, B &cir& NOt L &cir& NOt are driven independently of each other. This ensures that if an error occurs, the internal weighting circuit BWS of the internal bit lines BL, B &cir& NOt L &cir& NOt in which the error occurs is prevented from flipping.