Method and means for interfacing a system control unit for a multi-processor system with the system main memory.

摘要

In a multi-processing computer system including a plurality of central processing units (CPUs) and input/output (I/O) units, a system memory including a plurality of independently accessible DRAM-based memory units, and a system control unit (SCU) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of memory, dedicated interface means are provided for regulating the transfer of memory commands and associated data between the SCU and the various addressable segments comprising the main memory. The interfacing action is provided by accepting memory commands from the appropriate logic portion of the SCU, processing the commands to determine the availability of addressed memory segments, relaying executable memory commands, at synchronized intervals, to the segments of memory which need to be accessed, and transferring data, in the appropriate direction, as required by the memory commands. The dedicated interface is based on a modular macrocell-based array control unit (ACU) which processes memory commands from the system processors and other units by regulating timed addressing of valid memory segments and bi-directional on-the-fly data transfer to and from addressed segments in main memory under the control of command signals passing to and from the ACU.