| 摘要 |
A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At least one of slaves I/F 22-0, 22-1, . . . that control slave devices SV0-SV3 upon the request from master devices MS0-MS3 connected to interconnection bus BS via master I/Fs 21-0 through 21-3 has a constitution made of multiport slave I/F 23 corresponding to a multi-access function that allows simultaneous access from plural master devices MS0-MS3.
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