发明名称 VERFAHREN ZUR ERZEUGUNG VON PRUEFMUSTERN FUER EINEN BAUSTEIN
摘要 Modules (MD) arranged on a chip (CH) and which are accessible only from the leads (EXT) of the component (CH) are tested by means of test patterns which are produced for the modules (MD). For the test, these module patterns (MTM) are transformed into test patterns (BTM) which are applied to the leads (EXT) of the component (CH) and are such that the module test patterns (MTM) then appear at the leads (INT) of the modules (MD). The transformation is carried out by means of transmission functions (UF) which represent the connection paths from the leads (EXT) of the component to the leads (INT) of the modules (MD). The module test patterns (MTM) are converted by means of these transmission functions into component test patterns (BTM) which can then be applied to the leads of the components. Access to the leads of the modules (MD) is no longer necessary. The modules (MD) are circuits, e.g., adders or multipliers, etc., for which test patterns are already available. The networks followed by the connecting paths between the leads of the components and leads of the modules consist of circuit elements which do not falsify the logic of the signals to the leads of the components during transit to the leads of the modules.
申请公布号 DE3902835(A1) 申请公布日期 1990.08.02
申请号 DE19893902835 申请日期 1989.01.31
申请人 SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE 发明人 GLUNZ, WOLFGANG, DIPL.-ING.;JOHANSSON, MATS, DIPL.-ING.;ROTH, WOLFRAM, DIPL.-ING., 8000 MUENCHEN, DE
分类号 G01R31/3183 主分类号 G01R31/3183
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