发明名称 Final circuit for adder circuits which process 1-out-of-10-coded decimal digits
摘要 In the final circuit according to the subject of the invention, in partial circuit (30), the digits of the upper range (5 to 9) are not reduced by the number 5, but the digits of the lower range (0 to 4) are increased by the number 5. <IMAGE>
申请公布号 DE3902691(A1) 申请公布日期 1990.08.02
申请号 DE19893902691 申请日期 1989.01.30
申请人 MERKLE, PAUL, 7032 SINDELFINGEN, DE 发明人 MERKLE, PAUL, 7032 SINDELFINGEN, DE
分类号 G06F7/491;G06F7/50 主分类号 G06F7/491
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