发明名称 |
METHOD OF FERMING LOW RESISTANCE CONNECTION AT LOW RESISTANCE AREA OF VLSI DEVICE |
摘要 |
PURPOSE: To form a low-resistance connection in the resistance area of a VLSI device by preventing the occurrence of electrical disconnection by forming a titanium layer on the entire surface of a polycrystalline silicon layer and on the resistance area exposed in an opening and forming a titanium silicide by causing reaction between the titanium and the polycrystalline silicon layer. CONSTITUTION: An insulating layer 3 is formed on the surface of a silicon substrate 1 on which a resistance area 2 which is highly doped with an N- or P-type impurity is formed and a polycrystalline silicon layer 4 is deposited on the layer 3. After the silicon layer 4, an opening 5 is formed through the layers 4 and 3 so as to expose the selected part 6' of the resistance area 2 and a titanium layer 6 is formed by depositing titanium by sputtering except the vertical wall surfaces 8 of the insulating layer 3. Then the titanium layer is changed to a titanium silicide layer 7 by causing a reaction between the titanium in the layer 6 and the silicon in the underlying layer 4 by heating the layers 6 and 4 in a nitrogen atmosphere. Finally, a low-resistance connection is formed by depositing a tungsten silicide layer 9 on the vertical wall surfaces 8 of the insulating layer 3 and the titanium silicide layer 7. |
申请公布号 |
JPH02194524(A) |
申请公布日期 |
1990.08.01 |
申请号 |
JP19890022748 |
申请日期 |
1989.02.02 |
申请人 |
SANSEI ELECTRON CO LTD |
发明人 |
DEEJIE JIN;CHIYANNHIYUN KIMU;CHIYURUUJIN RII |
分类号 |
H01L27/04;H01L21/28;H01L21/285;H01L21/3205;H01L21/768;H01L21/822;H01L23/532 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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