Logic circuit having flip-flop function.

摘要

A logic circuit comprises a first terminal (D, D, 102a, 102b) for receiving an input data signal (D, D), a second terminal (C, 106) for receiving a clock signal (C, CLK*), a first latch circuit (32, 121-123) coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit (33, 124, 125) coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal (Q, Q, 103a, 103b) for outputting an output data signal (Q, Q) which is output from the second latch circuit, and a selecting part (30, 104, 121, 122) coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode.