| 摘要 |
PURPOSE:To attain a high-speed arithmetic processing by dividing an arithmetic unit into hierarchies in different ways, and adopting three selective ways to select all, to select none, or to select a single block lump of the arithmetic unit out of the divisions. CONSTITUTION:An arithmetic unit 2 is divided into the hierarchies according to the different ways, and in the respective hierarchies, a single block lump of the arithmetic unit 2 is selected, the all block lumps are selected, or no block lumps are selected. That is, a code inherent in itself is possessed by each arithmetic unit and the arithmetic unit, which indicates the existence of an event and requires communication, is detected at high speed out of the many arithmetic units, which independently and asynchronously operate, with the use of a single communication request line 3, prescribed pieces of selective lines 4, and a data bus 5, which can obtain a logical sum at every bit. Further the desired arithmetic unit is selected out of a host computer, and the communication between the arithmetic units on the present side and the host side is started. Thus the parallel computer system can be controlled at high speed. |
