发明名称 SYNCHRONIZING SIGNAL CORRECTING DEVICE
摘要 PURPOSE:To output an input synchronizing signal without being delayed from a normal time with a simple constitution by outputting a synchronizing signal corrected by a timer means even when it is decided that it is a synchronizing signal of a period being outside of an allowable range by a period deciding means. CONSTITUTION:When there is a fluctuation in a period of an input synchronizing signal B, and sections of a normal period are denoted as N, O and Q, and sections of off-specification are denoted as L and M, an output of a comparator 7 becomes L and a down-counter 11 is reset in the sections L, M. Accordingly, in this section, an output synchronizing signal C is outputted from the counter 11 irrespective of the signal B. In the sections N, O, a signal A becomes H. The signal C of the section N is outputted at a timing of the counter 11 irrespective of the signal B, and in the section O, this signal is outputted by an earlier one of a rise of the signal B and a timing of count-up of the counter 11. Even when it is decided to be a synchronizing signal of a period being outside of an allowable range by a period deciding means 3, a synchronizing signal corrected by a timer means 5 is outputted.
申请公布号 JPH02187978(A) 申请公布日期 1990.07.24
申请号 JP19890006260 申请日期 1989.01.14
申请人 OTANI DENKI KK 发明人 NAGASAKI KOICHI
分类号 G11B27/00;H04L7/00 主分类号 G11B27/00
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