| 摘要 |
PURPOSE:To accelerate the operation of a division, by repeating only a processing procedure of an addition of an intermediate residue and a divisor and accordingly obtaining the quotient of a digit and the intermediate residue. CONSTITUTION:A dividend A, a divisor B and -1 are set to registers 1, 2 and 5 as the initial value respectively. When the content of the register 5 is 1, the output of a selecting circuit 3 is equal to a complement of the divisor B. Accordingly an operator 4 performs a subtraction between the dividend A and the divisor B. In this case, an adder works to apply +1 to the contents of a counter 6. Thus the same operation is carried out as long as the content of the register 5 is 1, and +1 is applied continuously to the contents of the counter 6 to indicate continuously the execution of an arithmetic cycle preceding by two steps. In such a way, the carry delivered to a line 12 is set at 0, and then the arithmetic cycle preceding by one step is indicated. Here the circuit 3 delivers the contents of the register 2 as they are, and the operator 4 performs an addition of the dividend A and the divisor B. The result of this addition is always positive or 0 and also equal to the desired intermediate residue. At the same time, +1 is applied to the counter 6 and the contents of the counter 6 show the quotient. |
