发明名称 TRAP SYSTEM
摘要 PURPOSE:To eliminate an ineffective interruption of trap, by applying an interruption only in case the contents of a storage device or a register are changed due to a defect of a program. CONSTITUTION:When a memory changing trap is carried out, the address of a storage device MEM with which a program defect is expected is previously set to a trap address register 11. At the same time, the normal data corresponding to the address shown by the register 11 is set to a trap data register 12. The bit position 2 of a trap control register 10 is set at 1. Then the address in a memory address register 13 which is replaced by a coincidence circuit 20 with each writing to the MEM is collated with the address in the register 11. In case the coincidence is detected between both addresses and at the same time the discordance is detected between the writing data in a memory data register 14 corresponding to the relevant address and the normal data in the register 12, a defect of the program is decided. Thus an interruption is applied to an interrupting circuit via an AND circuit 40 and an OR circuit 50.
申请公布号 JPS5844546(A) 申请公布日期 1983.03.15
申请号 JP19810141010 申请日期 1981.09.09
申请人 HITACHI SEISAKUSHO KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;NIHON DENCHI KK;FUJITSU KK 发明人 TAKI YOSHIHARU;OKADA KATSUYUKI;OOTA YOSHIHISA;SAKATA HIRONOBU;URUSHIBARA TETSUO
分类号 G06F11/28;G06F11/36 主分类号 G06F11/28
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