| 摘要 |
A number of memory cells (20) are connected with bit line pairs. A circuit for charging and equalizing bit line pairs includes a pMOS transistor (13) for parallelly connecting with bit line pairs equalizing signal at read and write operation, first nMOS transistors (14,15) applied with the power supply voltage at gates, second nMOS transistors (16,17), and pMOS transistors (11,12) receiving the equalization pulse from a address transition detector and turns on the second nMOS transistros at read operation. The first/second nMOS transistors and pMOS transistors (11,12) are serially connected with bit line pairs.
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