| 摘要 |
PURPOSE:To reduce the leakage of signal between filters, by providing a separate clock driving circuit to a plurality of transversal filters. CONSTITUTION:A clock signal phi1' from a clock oscillator 18 is applied to each input terminal 16 of clock driving circuits 15a, 15b, 15c, and a clock signal phi2' from the clock oscillator 18 is given to each input terminal 16' of clock driving circuits 15a', 15b', 15c'. Further, clock signals phi1, phi2 from the clock driving circuits 15a, 15a' are respectively applied to clock input terminals 6a, 7a of a BBD of a filter Fa and the clock signals phi1, phi2 from the clock driving circuits 15b, 15b' are respectively given to clock input terminals 6b, 7b of a filter Fb. Further, the clock signals phi1, phi2 from clock driving circuits 15c, 15c' are respectively applied to clock input terminals 6c, 7c of a filter Fc. Of course, the clock line of the BBD of the filters Fa, Fb, Fc is made independent. A leakage signal is reduced to 1/hfe by an independent clock driving circuit. |
