| 摘要 |
Device for operating a redundant multiprocessor system for the control of an electronic signal mechanism. A coordination processor (ER) assigns to each operation control area processor (BR1, BR2) an operating address ("07", "08"), transmits this by means of a module address ("87", "88") to the processors and provides the processors with the data required for process control. The operation control processors (BR1, BR2) communicate with one another and with the coordination processor using the operating addresses allocated to them. If the coordination processor (ER) detects the failure of an operation control processor (BR1), and if an operational standby processor (BRR) is available, then the coordination processor assigns the operating address ("07") of the failed processor (BR1) to this processor (BRR) by addressing it via its module address ("89"), provides it with the relevant data for process control and includes it as the new operation control processor in the processor network. The remaining operation control processors (BR2) communicate with the previous standby processor (BRR) using the operating address ("07") allocated to the previous operation control processor (BR1) and now to the previous standby processor (BRR) without being informed that anything has changed in the hardware of the processor network as a result of the failure of a processor (BR1) and the activation of a standby processor (BRR). <IMAGE> |
