发明名称 FRAME PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent frame step-out occurring in spite of the normal operation of a circuit by providing a selector circuit to switch a frame to the one to which the load signal of a window generation circuit is inputted when a power source is applied and the cutoff of an input signal is recovered. CONSTITUTION:When the power source is applied and the cutoff of the input signal is recovered, the selector circuit 5 selects the frame FP1 generated from an input clock CLK1 by the input of a power-on-reset signal POR and an input signal cutoff detecting signal REC, and a counter 7 in the WIND (window) generation circuit 6 is loaded by the frame. Therefore, it is possible to align the phase of the frame FP1 generated from the input clock CLK1 with that of the frame FP2 generated from the output clock CLK2 of a PLL2. In such a way, the phases between the frames can be set at the optimum level when the power source is applied and the cutoff of the input signal is recovered, and it is possible to prevent malfunction such as a code error in a device as a whole due to the step-out of the frame while performing an operation occurring.
申请公布号 JPH02166934(A) 申请公布日期 1990.06.27
申请号 JP19880320675 申请日期 1988.12.21
申请人 HITACHI LTD;HITACHI COMMUN SYST INC 发明人 YAMADA IZURU;TAMAKOSHI MASASHI
分类号 H04J3/06;H04L7/00;H04L7/10 主分类号 H04J3/06
代理机构 代理人
主权项
地址