发明名称 KOSOKUFUURIEHENKANNOENZANSOCHI
摘要 <p>PURPOSE:To decrease the multiplying frequency and to shorten the arithmetic time by performing a butterfly operation with high efficiency after sorting the phase revolution factors into two types requiring no multiplication and two types requiring multiplication. CONSTITUTION:The read number data are successively impressed to a multiplexer 5 via input terminals 1 and 3 and then delivered after selecting either one of arithmetic units 6-10 in response to the contents of an integer part P. That is, the unit 6 performs the addition/subtraction in the case of type 1 where P is ''0'', and the unit 7 performs the addition/subtraction in the case of type 2 where P is ''2''. The units 8 and 9 perform operations in the case of type 3 where P is ''4'' or ''6''. Then the unit 10 performs an operation in the case of type 4 where P is >=8. As a result of such operations, no multiplication is needed with types 1 and 2, and the multiplying frequency of the type 3 is reduced down to half compared with the conventional operation. Thus the arithmetic time is shortened.</p>
申请公布号 JPH0228187(B2) 申请公布日期 1990.06.21
申请号 JP19830078823 申请日期 1983.05.04
申请人 VICTOR COMPANY OF JAPAN 发明人 TANAKA YOSHIAKI;INAMI MAMORU;OOTSUKI YOSHIKI
分类号 G06F17/14 主分类号 G06F17/14
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