发明名称 PIPELINE ARITHMETIC UNIT
摘要 <p>PIPELINE ARITHMETIC UNIT A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders are employed which accept two carry inputs and develop two carry outputs. The resulting number of individual cells is reduced to approximately half of those in the prior embodiment. In still another embodiment, switch means are included in each cell to delete the reclocking and in still another embodiment, the adders in the diagonal of the pipeline adder arc provided with additional inputs to permit use of the pipeline adder in recursive addition applications. In still another embodiment, tile cells are permitted to output the inverse of the intended signal, reducing thereby the physical realization of the cells and increasing the speed of the cells.</p>
申请公布号 CA1270569(A) 申请公布日期 1990.06.19
申请号 CA19870533466 申请日期 1987.03.31
申请人 AMERICAN TELEPHONE AND TELEGRAPH COMPANY 发明人 CASH, GLENN L.;HATAMIAN, MEHDI;LIGTENBERG, ADRIANUS
分类号 G06F7/53;G06F7/50;G06F7/508;G06F7/52;G06F7/527;(IPC1-7):G06F7/50 主分类号 G06F7/53
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