PHASE SYNCHRONIZING OSCILLATION CIRCUIT

摘要

PURPOSE:To reduce the fluctuation of the output frequency sepite the input of clock signals of different phases by connecting an LPF to a phase comparator by performing the control so as to secure the synchronization between the phase of the output signal of a frequency divider and the phase of a switched clock signal. CONSTITUTION:When a switch signal CH changes, a selector 1 selects a reference clock CK2 having a 36 deg. phase difference out of a reference clock signal CK1 and sends it to a phase comparator 7. An AND gate 17 secures an AND between reference clock signal S1 and S2, and outputs a clock signal S3. A frequency divider 13 is cleared by the output signal S4 of a pulse width conversion circuit 19 and restarts a dividing action when no pulse of the S4 exists any more. Then the phase of the output signal S5 is synchronous with the phase of the signal CK2. The output of the comparator 7 gets out of a synchronizing state in a moment right after the switch of clocks. In this case, however, the fluctuation of the output frequency can be suppressed for a voltage control oscillator 11 since the output change of an LPF 9 requires a sufficiently long time compared with a phase comparison period.