| 摘要 |
PURPOSE:To compensate for a delay time between output circuits caused by the length of each fixed wiring by providing different resistance elements corresponding to the length of each fixed wiring before and after an output circuit. CONSTITUTION:A numeral 10 represents the main body of the chip of a semiconductor integrated circuit device. A numeral 11 represents a gate array region constituted of inner circuits. Numerals 12-15 represent exclusive RAM regions which are provided in the chip beforehand. A numeral 16 represents output circuit region which is provided for driving the outside of an LSI. A numeral 17 represents an input circuit region which is provided for driving the inside of the LSI. A numeral 18 is a fixed wiring region which is provided for connecting the circuit in the gate array and each output circuit. A numeral 19 represents a resistance element which is provided for compensating for the difference in delay times caused by the difference in lengths of the wirings in the fixed wiring regions between the inner circuits and the output circuits. The resistance element 19 which is provided at each output circuit region 16 is arranged for compensating for parasitic capacitance due to the length of the wiring in each wiring region 18. The element 19 has the different resistance value in correspondence to each fixed wiring region 18. |
