发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To avoid the effect of circuit capacitance, by charging and discharging a load capacitance connected to an output terminal with gate control, through the connection of a circuit having level shift function, between each input/output terminal of a circuit constituting an NOR logic and a gate of normal conduction type. CONSTITUTION:A circuit constituting an NOR logic is provided with a gate consisting of a plurality of normal conduction type FETT1-Tn, the drains are connected in common to a load FETTL and also to output terminals OUT1- OUTm. The sources of the FETT1-Tn are connected in common, and a level shiaft circuit consisting of capacitors C1-Cn and diodes connected to constant current source FETTD1-TDn is connected between the gate of the FETT1- Tn and n sets of input terminals IN1-INn. The load capacitance connected to the terminals OUT1-OUTn is charged and discharged through the control of gate, allowing to make the manufacture of capacitors C1-Cn easy, to eliminate the effect and to make the operation of circuit stable.
申请公布号 JPS5862939(A) 申请公布日期 1983.04.14
申请号 JP19810161534 申请日期 1981.10.09
申请人 HITACHI SEISAKUSHO KK 发明人 HAYASHI TAKEHISA;MASAKI AKIRA;TANAKA HIRONORI;YAGIYUU MASAYOSHI
分类号 H03K19/0952;H03K19/0956 主分类号 H03K19/0952
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