| 摘要 |
A multiple-input digital filter capable of filtering a plurality of digital input signals with a single filtering device first latches the input signals and then sequentially selects each of the digital input signals for output to a counter circuit. The counter circuit, which is preset by the previous count value for the corresponding digital input signal, counts up or down depending on the digital input signal. When the count value reaches its maximum, a decision value signal is set for the corresponding digital input signal until the count value for that digital input signal returns to the minimum value. The count values are stored in a shift register which supplies the count value corresponding to the digital input signal as a preset value to the counter. A second shift register stores the decision values corresponding to each of the digital input signals which are then latched for simultaneous output.
|
