Pipeline computer system having order preservation.

摘要

A method and apparatus for preserving the write order in an interruptible pipeline processor wherein each bus transaction is provided with an acknowledgment after the transaction. If the acknowledgment indicates a failed transaction, a rejected signal is generated by the origination of the transaction which causes the effects of the subsequent operation to be cancelled. The transaction sequence is restarted, beginning with the previously failed transaction, and continues with a preserved transaction write order.