| 摘要 |
PURPOSE:To perform multiplication and division at a high speed by successively operating remainders Rj while j=l, l--1 and solving R1+deltan (delta. integer) when integers M1, M2, and (n) (0<=M1<n) are inputted to solve (M1XM2)+n. CONSTITUTION:When j=l, l-1-1, remainders Rj are summed up by a carrier comulative adder 1 successively, and the addition result Rj is stored in master/ slave type registers 2 and 3 separately. The values Rj of the registers 2 and 3 are sent to an adder 7, and when that propagation of a carrier by the adder 7 is completed is reported from a carrier inspection part 22, a control part 9 decides that R1<0, and sends a compensation calculation signal to a calculation part 4 for a quotient Ij. Thus, a remainder R1+on (n; integer) is found to perform multiplication and division at the same timing, finding the quotient and remainder speedily. |
