| 摘要 |
<p>PURPOSE:To reduce an integration circuit to one and to prevent the integration circuit from being affected by offset voltage drift by subtracting the double output of the integration circuit that is the intermediate result of the output of the integration circuit from the final result of the output of the integration circuit. CONSTITUTION:The output of a sample and hold circuit 4 is equal to an area where an input signal is segmented from the front end of a gate G 1 to the center of the gate, and the output of the integration circuit 3 is equal to the area where the input signal is segmented from the front end of the gate G 1 to the rear end of it. Therefore, the output of the integration circuit 3 goes to double the output of the sample and hold circuit 4 when the center of the input signal X0 is equal to that of the gate. Thereby, the output of the sample and hold circuit 4 is doubled by a scaler 6, and the output of the integration circuit 3 is subtracted at a subtractor 7. In such a way, a signal with amplitude proportional to the difference of the center of the input pulse signal X0 and that of the gate is outputted from the subtractor 7.</p> |
