发明名称 TRUTH TABLE LOGICAL SIMULATION METHOD
摘要 PURPOSE:To directly execute logical simulation at high speed by providing a step to convert input information to a truth table and a step to calculate a part to be the value of 0 or 1. CONSTITUTION:In the step to convert the input information to a logic circuit model expressed in the truth table, for the logical value 1 of the input information, 10 and 0 and the value of 01, 0 or 1 are converted to 00. An AND with the respective sets of certain input values is obtained and compared with the original input information. Accordingly, it can be regarded that the value of 0 or 1 can be coincident with the values of 0 and 1 and the value of 0 or 1. Next, in the step to calculate the part to go to the value of 0 or 1, when the truth table is changed, the OR is obtained for the sets of output values. Thus, the calculated result of the part, which can simultaneously obtain the logical value 1, logical value 0 and the logical value 1 or 0 and the value of the logical value 0 or 1, goes to 11 and this result can be outputted as the value of 0 or 1.
申请公布号 JPH02130645(A) 申请公布日期 1990.05.18
申请号 JP19880283581 申请日期 1988.11.11
申请人 HITACHI LTD 发明人 YAMADA YASUNORI;AMANO NOBUTAKA;OBATA MAKOTO
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
代理机构 代理人
主权项
地址