发明名称 BIT PHASE SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To detect a data slip automatically and to avoid the slip without using any frame by adding a circuit comparing the relation of phase between a write ring counter and a readout ring counter and outputting a reset pulse when the phase is nearly in phase with an elastic storage. CONSTITUTION:A T-FF22 is reset by an output pulse from a terminal Qa and outputs from both terminals Qb, Qa are ORed and the result is fed to the T-FF 22, then a pulse having an interval between leading edges of the pulses from both the output terminals Qb, Qa is outputted and segmented by a write clock to output a pulse synchronously with the write clock and the pulse represents a detection range. The pulse representing the detection range and the pulse from the output terminal of the write ring counter are ANDed, then a reset pulse is outputted from the RES terminal of a phase comparator 20 when the relation of phase enters the detection range. Thus, a correct data is outputted.</p>
申请公布号 JPH02125542(A) 申请公布日期 1990.05.14
申请号 JP19880278977 申请日期 1988.11.04
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 OOTSUKA YOSHIHIRO
分类号 H04L7/00 主分类号 H04L7/00
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