| 摘要 |
The train of pseudo-analog signals delivered by a logic circuit is sampled with a sampling clock of frequency n times larger than the tempo of the said train. The samples are grouped into binary words of n bits, with each sampling, the highest order bit of the current binary word is deleted, the remaining (n-1) bits are shifted and the bit resulting from the sampling becomes the low order bit. Likewise, with each sampling, the current binary word is converted into an analog value. The method also applies to a set of pseudo-analog signals. <IMAGE>
|
