| 摘要 |
PURPOSE:To attain a stable synchronization detection with high accuracy in a short time by providing a means discriminating it as synchronization when the number of original oscillation signal pulses appearing in one period of an input signal reaches a specified time. CONSTITUTION:The circuit consists of a counter 6, a frequency divider 12 dividing an input signal frequency by 1/2, a reset circuit 8 resetting the counter, a comparator 7 discriminating whether or not the counted value is within a specified value and a latch circuit 11 latching the comparator output with a signal subjected to 1/2 frequency division. In this case, the output frequency of a voltage controlled oscillator 4 is a multiple of (n) of the frequency of the comparison input pulse signal PDT. For example, suppose that the value (n) is 4, then the comparison value for the comparator 7 is set to 2n-1, the comparator 7 compares the output of the counter 6 with the comparison value '7' at all times and gives an output when they are identical. The latch circuit 11 latches the output of the comparator 7 at the rise of a frequency division pulse signal PDD, and the latched signal is a synchronization detection signal. Thus, stable synchronization detection is attached. |
