发明名称 |
SUBSTRATE BIAS GENERATING CIRCUIT |
摘要 |
PURPOSE:To decrease the power consumption in a waiting mode of a DRAM by applying the substrate potential detection output to each gate electrode of a control MOS transistor. CONSTITUTION:When a substrate potential is kept at a low level, the output of a substrate potential detecting circuit 7 connected to a power line 6 outputs a potential that can sufficiently turn on the control MOS transistors 11-13. Therefore the high frequency output of a ring oscillator 1 is applied to a driver 2, and the potential of the line 6 is quickly raised up. While the output of the circuit 7 is gradually reduced when the substrate potential is reduced down to a satisfactory level. Then the resistance values of the transistors 11-13 are increased. As a result, the power consumption of the oscillator 1 is reduced and at the same time the power consumption of a driver 2 is also reduced. Then the power consumption can be reduced in a waiting mode of a DRAM. |
申请公布号 |
JPH02121188(A) |
申请公布日期 |
1990.05.09 |
申请号 |
JP19880271041 |
申请日期 |
1988.10.28 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
FUJIWARA ATSUSHI;SHIBAYAMA AKINORI |
分类号 |
G11C11/407;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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