| 摘要 |
<p>PURPOSE:To improve the performance of a system by allowing a system board to identify data bus width outputted from an option board and driving a microprocessor by a clock appropriate for the data bus width. CONSTITUTION:The title information processor is provided with the 1st decoder 21 for converting the address signal 1a of a selected and accessed I/O adaptor out of plural I/O adaptors 31 to 33 into the 1st selection signal 1c, the 2nd decoder for converting a status signal 1b into the 2nd selection signal 1d, a synchronous circuit 23 for thinning a reference clock by the 1st and 2nd selection signals 1c, 1d, and a bus control part 14 for identifying the data bus width by deciding whether an external control signal (f) outputted from the selected I/O adaptor at the decay timing of an address latch enable signal formed from the status signal 1b outputted from a microprocessor 11 synchronously with the thinned clock is high or low. The microprocessor 11 is riven by a cycle appropriate for the processing speed of the selected I/O adaptor. Thus, the system with high performance can be obtained.</p> |
