| 摘要 |
<p>The disclosed two stage address decoder circuit (AD) for 1/64 decoder operation includes a first stage comprised of two predecoder circuits (PDP; PDQ) operable to develop predecoded output signals (P0, ..., P7; Q0, ..., Q7) in response to input address signals (A1, ..., A3; A4, ..., A6) and the corresponding inverted address signals. Each predecoder circuit consists of a low power high speed Differential Cascode Current Switch (DCCS) tree with its associated current source. The second or final decode stage (FD) is comprised of a plurality of final decoding circuits (FD1, ..., FD64). Each FD circuit consists of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one couple of said predecoded output signals (P1, Q1; ...; P8, Q8). Final decoder circuits supplies a final decoded output signals (X1, ..., X64) to drive the word lines (WL1, ..., WL64) of a memory cell array (MA). The switched current source is triggered by a control signal (SWL) supplied by a clock generator (CG) so that the FD circuits consume power only when the control signal is active. The use of a DCCS tree in the predecoder and of a switched OR gate in the final decoder circuit gives the address decoder circuit a competitive speed-power product with a safe and glitchless behavior.</p> |
