| 摘要 |
<p>A semiconductor memory device having a decoder circuit (DEC), the decoder circuit including a load transistor (T1), a NAND gate circuit (D), i.e. a driver circuit serially connected to the load transistor (T1) and including a plurality of driving transistors (T2 to T5) serially connected to each other, an inverter (IV) connected to the node (N1) formed between the load transistor (T1) and the NAND gate circuit (D), and an additional load current increasing means (T8) connected to the node (N1) or to a contact portion formed between two transistors arranged adjacently to each other in the NAND gate circuit, the load current increasing means (T8) being operable only in the reading mode for increasing the load current and thus to increase the threshold voltage level of the decoder circuit up to about Vcc/2, thereby preventing erroneous operation of the decoder and the memory cell array.</p> |
